Semiconductor package with clock sharing and electronic system including the same

A semiconductor package, comprising:

• a first data clock signal line configured to transmit a first data clock signal, the first data clock signal being received from the outside of the semiconductor package and the first data clock signal line being branched into n lines, where n is an integer greater than or equal to 2;
• a second data clock signal line configured to transmit a second data clock signal, the second data clock signal being received from the outside of the semiconductor package and the second data clock signal line being branched into m lines where m is an integer greater than or equal to 2;
• a first data bus configured to transmit data of a first data group;
• a second data bus configured to transmit data of a second data group;
• a third data bus configured to transmit data of a third data group;
• a fourth data bus configured to transmit data of a fourth data group;
• and
• a memory device coupled to the first and second data clock signal lines and the first through the fourth data buses,
• wherein the memory device includes,
• first data pads being connected to the first data bus,
• second data pads being connected to the second data bus,
• third data pads being connected to the third data bus,
• fourth data pads being connected to the fourth data bus,
• a first clock pad being connected to the first data clock signal line, the first clock pad being configured to receive the first data clock signal and the first data pads being configured to receive the data of the first data group based on the first clock pad receiving the first data clock signal,
• a second clock pad being connected to the first data clock signal line, the second clock pad being configured to receive the first data clock signal and the second data pads being configured to receive the data of the second data group based on the second clock pad receiving the first data clock signal,
• a third clock pad being connected to the second data clock signal line, the third clock pad being configured to receive the second data clock signal and the third data pads being configured to receive the data of the third data group based on the third clock pad receiving the second data clock signal, and
• a fourth clock pad being connected to the second data clock signal line, the fourth clock pad being configured to receive the second data clock signal and the fourth data pads being configured to receive the data of the fourth data group based on the fourth clock pad receiving the second data clock signal.

A mobile electronic device, comprising:

• a memory device;
• and
• a memory controller configured to transmit a first data clock signal to the memory device,
• wherein the memory device includes,
• a first data clock signal line configured to receive the first data clock signal, the first data clock signal line being branched into n lines, where n is an integer greater than or equal to 2,
• first data pads configured to transmit and receive data of a first data group,
• second data pads configured to transmit and receive data of a second data group,
• a first clock pad being connected to the first data clock signal line, the first clock pad configured to receive the first data clock signal and the first data pads being configured to receive the data of the first data group based on the first clock pad receiving the first data clock signal, and
• a second clock pad being connected to the first data clock signal line, the second clock pad configured to receive the first data clock signal and the second data pads being configured to receive the data of the second data group based on the second clock pad receiving the first data clock signal.