Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
• a plurality of insulation layers arranged between the plurality of gate electrodes;
• an upper insulation layer arranged on a first gate electrode, which is an uppermost gate electrode of the plurality of gate electrodes;
• a plurality of channel structures penetrating through the upper insulation layer, the plurality of gate electrodes, and the plurality of insulation layers in the first direction, each of the plurality of channel structures including a plurality of layers;
• a pair of word line cuts separating each gate electrode of the plurality of gate electrodes and separating each insulation layer of the plurality of insulation layers in a second direction parallel to the upper surface of the substrate;
• and
• a plurality of string selection line cut insulation layers arranged between the pair of word line cuts and separating the upper insulation layer in the second direction to form a separated upper insulation layer and separating the first gate electrode in the second direction to form a separated first gate electrode,
• wherein each of the plurality of string selection line cut insulation layers includes a sidewall spaced apart from a sidewall of the separated upper insulation layer.

A semiconductor memory device comprising:

• a plurality of gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and each of the plurality of gate electrodes comprising a gate conductive layer and a first barrier layer covering the gate conductive layer, each of the plurality of gate electrodes comprising:
• at least one ground selection gate electrode arranged on the substrate,
• a plurality of word line gate electrodes arranged on the at least one ground selection gate electrode, and
• at least one string selection gate electrode arranged on the plurality of word line gate electrodes;
• a plurality of insulation layers arranged between the plurality of gate electrodes;
• an upper insulation layer arranged on the at least one string selection gate electrode;
• a plurality of channel structures penetrating through the upper insulation layer, the plurality of gate electrodes, and the plurality of insulation layers in the first direction, each of the plurality of channel structures including a plurality of layers;
• a pair of word line cut insulation layers, wherein the plurality of gate electrodes and the plurality of insulation layers are disposed between the pair of the word line cut insulation layers spaced apart from each other in a second direction parallel to the upper surface of the substrate;
• and
• a plurality of string selection line cut insulation layers arranged between the pair of word line cut insulation layers and separating each of the upper insulation layer and the at least one string selection gate electrode in the second direction,
• wherein the first barrier layer included in the at least one string selection gate electrode is between the upper insulation layer and each of the plurality of the string selection line cut insulation layers.