Low latency adaptive clocking

An apparatus comprising:

• a first power supply rail to provide a first power;
• a second power supply rail to provide a second power;
• a third power supply rail to provide a third power;
• a voltage divider coupled to the first, second, and third power supply rails;
• a bias generator coupled to voltage divider and the third power supply rail;
• an oscillator coupled to the bias generator and the first supply rail;
• and
• a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.

An apparatus comprising:

• a first power supply rail to provide a first power;
• a second power supply rail to provide a second power;
• a third power supply rail to provide a third power;
• a voltage divider coupled to the first, second, and third power supply rails;
• a digital loop filter coupled to the voltage divider and the third power supply rail;
• an oscillator coupled to the digital loop filter and the third power supply rail;
• a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail;
• and
• a time-to-digital converter (TDC) coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail.

A system comprising:

• a memory;
• a processor coupled to a memory, the processor including:
• a first power supply rail to provide a first power;
• a second power supply rail to provide a second power;
• a third power supply rail to provide a third power;
• a voltage divider coupled to the first, second, and third power supply rails;
• a bias generator coupled to voltage divider and the third power supply rail;
• an oscillator coupled to the bias generator and the first supply rail;
• and
• a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail;
• and
• a wireless interface to allow the processor to communicate with another device.

A system comprising:

• a memory;
• a processor coupled to a memory, the processor including:
• a first power supply rail to provide a first power;
• a second power supply rail to provide a second power;
• a third power supply rail to provide a third power;
• a voltage divider coupled to the first, second, and third power supply rails;
• a digital loop filter coupled to the voltage divider and the third power supply rail;
• an oscillator coupled to the digital loop filter and the third power supply rail;
• a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail;
• and
• a time-to-digital converter (TDC) coupled to the digital loop filter, wherein the TDC is coupled to the first power supply rail;
• and
• a wireless interface to allow the processor to communicate with another device.