Communication chipset, communication device and protocol offload method for automatic address allocation

A protocol offload method for automatic address allocation, the method performed in a communication chipset included in a communication device capable of data communication with other devices through a network and connected to a controller of the communication device through a transmission and reception bus, the method comprising the steps of:

• setting address setting modes of a plurality of registers on the basis of data received from the controller controlling the communication device through a serial bus or a parallel bus, by a controller-interface;
• automatically setting an IP address using a network packet received through state transition that is different for each set address setting mode, and setting a lifetime-counter of the IP address with a time corresponding to a time stamp determined through the network packet, under the control of an IP address creation control module provided with a state machine configured as hardware logic;
• and
• automatically re-setting the set IP address using a network packet received through the network according to a sensing signal created as a time specified according to setting of the lifetime-counter is elapsed, under the control of the IP address creation control module, wherein
• the setting step includes the steps of:
• enabling, when the address setting mode set by the controller through the serial bus or the parallel bus is an automatic-search address mode or a stateless address auto-configuration mode, address configuration of a first address configuration offload module so that the IP address can be configured through an ICMP packet, by the IP address creation control module;
• and
• receiving the ICMP packet processed by hardware logic for the network packet of the network and configuring the IP address according to a message type of the ICMP packet, as the address configuration is enabled, by the first address configuration offload module provided with the hardware logic.