Apparatus containing circuit-protection devices

An apparatus, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective set of strings of series-connected memory cells of the plurality of strings of series-connected memory cells;
• peripheral circuitry for access of the array of memory cells;
• a first transistor comprising a control gate connected to a first control line, a first source/drain connected to a first contact for connection to the peripheral circuitry, and a second source/drain connected to a second contact for connection to a first data line of the plurality of data lines;
• a second transistor comprising a control gate connected to a second control line, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the first data line;
• a third transistor comprising a control gate connected to the first control line, a first source/drain connected to a fourth contact for connection to the peripheral circuitry, and a second source/drain connected to a fifth contact for connection to a second data line of the plurality of data lines;
• a fourth transistor comprising a control gate connected to the second control line, a first source/drain connected to the fifth contact, and a second source/drain connected to a sixth contact for connection to the common source, wherein the common source is further selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the second data line;
• and
• a fifth transistor comprising a control gate connected to the second control line, a first source/drain connected to the second contact, and a second source/drain connected to the fifth contact.

An apparatus, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective set of strings of series-connected memory cells of the plurality of strings of series-connected memory cells;
• peripheral circuitry for access of the array of memory cells;
• a first circuit-protection unit having a first node formed in a first active region and a second node formed in a second active region contiguous with the first active region, wherein the first circuit-protection unit comprises:
• a first transistor comprising a control gate connected to a first control line, a first source/drain connected to a first contact for connection to the peripheral circuitry, and a second source/drain connected to a second contact for connection to a first data line of the plurality of data lines;
• and
• a second transistor comprising a control gate connected to a second control line, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the first data line;
• a second circuit-protection unit having a first node formed in the first active region and a second node formed in a third active region contiguous with the first active region and separated from the second active region by an isolation region, wherein the second circuit-protection unit comprises:
• a third transistor comprising a control gate connected to the first control line, a first source/drain connected to a fourth contact for connection to the peripheral circuitry, and a second source/drain connected to a fifth contact for connection to a second data line of the plurality of data lines;
• and
• a fourth transistor comprising a control gate connected to the second control line, a first source/drain connected to the fifth contact, and a second source/drain connected to a sixth contact for connection to the common source, wherein the common source is further selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the second data line;
• and
• a fifth transistor comprising a control gate connected to the second control line, a first source/drain connected to the second contact, and a second source/drain connected to the fifth contact.