Semiconductor integrated circuit and withstand voltage test method

A semiconductor integrated circuit comprising:

• a chip formation region having a laminated structure in which a plurality of wiring layers are laminated;
• a plurality of seal rings disposed to surround an outside of the chip formation region, having an identical laminated structure with the chip formation region, and formed of metal wiring;
• a plurality of relay regions disposed at the outside of the chip formation region, having an identical laminated structure with the chip formation region, and formed of metal wiring;
• a plurality of vias formed between the wiring layers adjacent to each other;
• and
• a voltage application region and a voltage applying pad provided on a wiring layer which is positioned farthest from a substrate and on which the chip formation region and one of the seal rings are formed, among the plurality of wiring layers,
• wherein the voltage application region and the voltage applying pad form withstand voltage measuring wiring lines insulated from each other and different from each other by connecting one of the seal rings and one of the relay regions through one of the vias, and
• the withstand voltage measuring wiring lines different from each other are configured to apply a voltage between insulated seal rings provided on the wiring layers adjacent to each other by applying a voltage between the voltage application region and the voltage applying pad.