US 2020/0264984 A1 · PARTIAL CACHING OF MEDIA ADDRESS MAPPING DATA

Abstract

An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.

Claims20

Dependent claims

A method comprising:

reading a first entry from a first memory component, the first entry associated with a first logical address, the first entry including a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component, wherein the segment of the logical-to-physical address map includes a second entry associated with the first logical address;
and
writing, based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component, a second physical address to the second entry in the first memory component.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

read a first entry from a first memory component, the first entry associated with a first logical address, the first entry including a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component, wherein the segment of the logical-to-physical address map includes a second entry associated with the first logical address;
and
write, based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component, a second physical address to the second entry in the first memory component.

A system comprising:

a volatile memory component;
a non-volatile memory component;
and
a processing device, operatively coupled with the volatile memory component and the non-volatile memory component, to:
read a first entry from the volatile memory component, the first entry associated with a first logical address, the first entry including a first physical address to a segment of a logical-to-physical address map in the non-volatile memory component and an indication of whether the segment of the logical-to-physical address map is stored in the volatile memory component, wherein the segment of the logical-to-physical address map includes a second entry associated with the first logical address;
and
write, based on a determination from the indication that the segment of the logical-to-physical address map is stored in the volatile memory component, a second physical address to the second entry in the volatile memory component.

4 more elements

Dependencies are inferred from the claim text.

Partial caching of media address mapping data

Life of this patent

Partial caching of media address mapping data

Life of this patent

Abstract

Claims20