Power management for partial cache line sparing

An electronic processing system, comprising:

• a memory controller;
• a first memory communicatively coupled to the memory controller;
• a processor communicatively coupled to the memory controller;
• a second memory communicatively coupled to the processor;
• and
• logic communicatively coupled to the memory controller, the first memory, the processor, and the second memory to:
• store cache line spare information in the first memory,
• detect a first power state change for the first memory, and
• save the cache line spare information to the second memory based on the detected first power state change.

A semiconductor package apparatus, comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
• store cache line spare information in a first memory,
• detect a first power state change for the first memory, and
• save the cache line spare information to a second memory based on the detected first power state change.

A method of cache line sparing, comprising:

• storing cache line spare information in a first memory;
• detecting a first power state change for the first memory;
• and
• saving the cache line spare information to a second memory based on the detected first power state change.

At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:

• store cache line spare information in a first memory;
• detect a first power state change for the first memory;
• and
• save the cache line spare information to a second memory based on the detected first power state change.