Strong arm latch with wide common mode range

A system comprising:

• a memory;
• a processor coupled to the memory, the processor having a receiver including a sense amplifier latch, wherein the sense amplifier latch comprises:
• a first sampler to sample an input with a first clock, and to provide a sampled output on a first node;
• a strong arm latch (SAL) to receive the first sampled output on the first node, and to sample the first sampled output according to a second clock;
• and
• a first digital-to-analog converter (DAC) coupled to the first node, wherein the first DAC is to adjust a common mode of the first sampled output according to a digital control to the DAC;
• a second sampler to sample a second input with the first clock, and to provide a second sampled output on a second node;
• and
• a second DAC coupled to the second node, wherein the second DAC is to adjust a common mode of the second sampled output according to the digital control to the second DAC;
• wherein the SAL comprises:
• a first differential circuitry to receive the first and second sampled inputs;
• a second differential circuitry to receive the first and second sampled inputs;
• and
• a latch circuitry coupled to the first and second differential circuitries;
• and
• a wireless interface to allow the processor to communicate with another device.