US 2020/0091189 A1Published application

Memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsKwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori

Life of this patent

Estimating the term…

Loading patent…

Abstract

A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Claims17

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming a first impurity region by injecting impurity to at least a portion of a semiconductor substrate;
forming a substrate sacrificial layer and a plurality of supporting regions on an upper surface of the semiconductor substrate;
forming a semiconductor layer on the substrate sacrificial layer and the plurality of supporting regions, the semiconductor layer including a second impurity region;
stacking alternately a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor layer;
forming a plurality of channel holes penetrating the plurality of sacrificial layers and the plurality of insulating layers and extending to the first impurity region;
remaining the second impurity region by removing a portion of the semiconductor layer;
forming a gate insulating layer and a channel layer in each of the plurality of channel holes;
forming a word line cut dividing the plurality of sacrificial layers and the plurality of insulating layers into a plurality of regions;
forming a substrate opening by removing a substrate sacrificial layer and a portion of the gate insulating layer;
and
filling the substrate opening with a semiconductor material.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/692,385Filed 22 Nov 2019
Priority: KR 10-2016-007784022 Jun 2016
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B
Electronic memory devices

Family

Application15/393,775Division · filed 29 Dec 2016
Application16/149,249Continuation · filed 2 Oct 2018
Application16/692,385Continuation
Application16/149,249Division
US 10,134,752 B2Related patent
US 10,522,562 B2Related patent
US 11,004,865 B2Related patent
US 2017/0373089 A1Published application
US 2019/0043886 A1Published application
US 2020/0091189 A1This patent

From the US filing history. Foreign family members aren’t listed.