Integrated circuit and layout design method
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorHirokazu Okano
Life of this patent
Estimating the term…
Abstract
According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.
Claims9
An integrated circuit comprising:
- a circuit provided with terminals;
- a plurality of circuit blocks provided with terminals;
- and
- a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.
A layout design method for an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, the layout design method comprising:
- determining circuit blocks to be connection destinations of respective wirings that run in parallel from the circuit so that any adjacent wirings at the terminals of the circuit are connected to different circuit blocks;
- and
- determining the arrangement of the respective wirings so that the respective wirings are connected to the determined circuit blocks of the connection destinations.
Dependencies are inferred from the claim text.