US 2020/0007130 A1 · Low Power Logic Circuit

Abstract

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Claims20

Dependent claims

A logic circuit comprising:

a first thin film transistor (TFT) having a first drain, a first gate, and a first source;
a second TFT having a second drain, a second gate, and a second source;
a third TFT having a third drain, a third gate, and a third source;
and
a fourth TFT having a fourth drain, a fourth gate, and a fourth source,
wherein the second source, the fourth gate, the third source, and the first drain form a first node,
wherein the fourth drain and the second drain form a second node,
wherein the fourth source, the second gate, and the third drain form a third node, and
wherein the third gate and the first gate form a fourth node.

6 more elements

Dependencies are inferred from the claim text.

Low Power Logic Circuit

Life of this patent

Low Power Logic Circuit

Life of this patent

Abstract

Claims20