Channel layer formation for iii-v metal-oxide-semiconductor field effect transistors (mosfets)

A method for forming a semiconductor device, the method comprising:

• forming isolation areas above a substrate and a trench between the isolation areas;
• forming a first buffer layer over the substrate, in contact with the substrate, and within the trench;
• forming a second buffer layer over the first buffer layer, in contact with the first buffer layer, and within the trench;
• forming a channel area including InP above a portion of the second buffer layer;
• removing the portion of the second buffer layer under the channel area, while keeping the second buffer layer in areas not overlapping with the channel area;
• forming a high-k gate dielectric layer above the first buffer layer and completely around the channel area;
• forming a gate electrode above the first buffer layer, completely around the high-k gate dielectric layer, and completely around the channel area;
• forming a source area above the second buffer layer, in contact with the second buffer layer, and adjacent to a first end of the channel area;
• and
• forming a drain area above the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area.

A computing device, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device or the processor includes a transistor comprising:
• isolation areas above a substrate to form a trench between the isolation areas;
• a first buffer layer over the substrate, in contact with the substrate, and within the trench;
• a second buffer layer within the trench over the first buffer layer, in contact with the first buffer layer;
• a channel area above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer, wherein the channel area includes an III-V material;
• a high-k gate dielectric layer above the first buffer layer and completely around the channel area;
• a gate electrode above the first buffer layer without overlapping the second buffer layer, completely around the high-k gate dielectric layer, and completely around the channel area;
• the source area above the second buffer layer, in contact with the second buffer layer, and adjacent to a first end of the channel area;
• and
• the drain area above the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area.