Self-aligned unsymmetrical gate (saug) finfet and methods of forming the same

A method of forming a semiconductor structure, the method comprising:

• forming a fin extending from a substrate, the fin having isolation regions along opposing sides of the fin;
• forming a first dielectric layer over the fin, the first dielectric layer having a first opening, the first opening exposing a first sidewall of the fin and extending above the fin;
• forming a first oxide layer in the first opening;
• forming a nitride layer over the first oxide layer;
• forming a second oxide layer over the nitride layer;
• forming a semiconductor layer over the second oxide layer;
• planarizing the first oxide layer, the nitride layer, the second oxide layer, and the semiconductor layer to remove the first oxide layer, the nitride layer, the second oxide layer, and the semiconductor layer from over the fin, wherein remaining portions of the first oxide layer, the nitride layer, the second oxide layer, and the semiconductor layer form a programming gate structure;
• removing the first dielectric layer;
• forming a second dielectric layer over the fin, the second dielectric layer having a second opening, the second opening exposing a second sidewall of the fin opposite the programming gate structure and extending above the fin;
• forming a gate dielectric layer in the second opening;
• forming a gate electrode layer over the gate dielectric layer;
• and
• planarizing the gate dielectric layer and the gate electrode layer to remove the gate dielectric layer and the gate electrode layer from over the fin, wherein remaining portions of the gate dielectric layer and the gate electrode layer form a switching gate structure.

A semiconductor device comprising:

• a semiconductor fin;
• a first gate structure on a first side of the semiconductor fin, the first gate structure comprising:
• a first oxide layer on a first sidewall of the semiconductor fin;
• a nitride layer on the first oxide layer;
• a second oxide layer on the nitride layer;
• and
• a semiconductor layer on the second oxide layer;
• and
• a second gate structure on a second side of the semiconductor fin opposite the first gate structure, the second gate structure comprising:
• a gate dielectric layer on a second sidewall of the semiconductor fin;
• and
• a gate electrode on the gate dielectric layer.