Vertical transistors with various gate lengths

A vertical transistor device, comprising:

• a first vertical transistor comprising a first channel region on a semiconductor substrate, wherein the first vertical transistor has a first gate length;
• a second vertical transistor comprising a second channel region on the semiconductor substrate, wherein the second vertical transistor has a second gate length longer than the first gate length;
• and
• bottom source/drain regions disposed adjacent bottom portions of each of the first and second channel regions;
• wherein a height of the bottom source/drain region corresponding to the first channel region is greater than a height of the bottom source/drain region corresponding to the second channel region.

A method for manufacturing a vertical transistor device, comprising:

• forming a plurality of vertical channel regions on a semiconductor substrate;
• forming at least two spacer layers around a first vertical channel region of the plurality of vertical channel regions, wherein the at least two spacer layers comprise a first spacer layer comprising a first material and a second spacer layer comprising a second material different from the first material;
• forming a single spacer layer around a second vertical channel region of the plurality of vertical channel regions, wherein the single spacer layer comprises the second material;
• selectively removing part of the first spacer layer to expose part of the first vertical channel region;
• and
• epitaxially growing a source/drain region around the exposed part of the first vertical channel region.