US 2020/0006549 A1Published application

Drain extended transistor

AssigneeTexas Instruments Incorporated

InventorsAlexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd

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Abstract

Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Claims23

Dependent claims

A drain extended transistor, comprising:

a body region in a semiconductor substrate, the body region including:
majority carrier dopants of a first type;
and a channel portion;
a source region in the semiconductor substrate, the source region adjacent the channel portion of the body region, the source region including majority carrier dopants of a second type;
an oxide structure that extends along a first side of the semiconductor substrate, the oxide structure including:
a first end spaced nearer the channel portion of the body region;
and a second end opposite the first end;
a drain region in the semiconductor substrate, the drain region including majority carrier dopants of the second type, wherein the second end of the oxide structure is adjacent the drain region;
a drift region, including:
a first drift region portion in the semiconductor substrate at the first side, the first drift region portion extending from the channel portion of the body region to the first end of the oxide structure, the first drift region portion including majority carrier dopants of the second type having a first dopant concentration;
and
a second drift region portion separated from the first side by at least a portion of the oxide structure, the second drift region portion extending from the first drift region portion to the drain region, the second drift region portion including majority carrier dopants of the second type having a second dopant concentration less than the first dopant concentration;
and
a gate structure, including a gate dielectric layer formed over the first side of the semiconductor substrate, and a gate electrode on the gate dielectric layer.

11 more elements

An integrated circuit (IC), comprising:

a semiconductor substrate, including:
a first side;
and a second side spaced from the first side along a first direction;
a first doped layer in the substrate, the first doped layer including majority carrier dopants of a first type;
and
a drain extended transistor, comprising:
a body region that extends along the first direction into the first doped layer from the first side, the body region including:
majority carrier dopants of the first type;
and a channel portion;
a source region that extends along the first direction into the first doped layer from the first side, the source region adjacent a first side of the channel portion of the body region, the source region including majority carrier dopants of a second type;
an oxide structure that extends along the first side, the oxide structure including:
a first end spaced along a second direction from the channel portion of the body region;
and
a second end;
a drain region that extends along the first direction into the first doped layer from the first side, the drain region including:
majority carrier dopants of the second type, and a first end adjacent the second end of the oxide structure;
and
a drift region, including:
a first drift region portion that extends along the first direction into the first doped layer from the first side, the first drift region portion extending along the second direction from the channel portion of the body region to the first end of the oxide structure, the first drift region portion including majority carrier dopants of the second type having a first dopant concentration;
and
a second drift region portion separated from the first side along the first direction by at least a portion of the oxide structure, the second drift region portion extending along the second direction from the first drift region portion to the drain region, the second drift region portion including majority carrier dopants of the second type having a second dopant concentration less than the first dopant concentration;
and
a gate structure, including a gate dielectric layer formed over the first side of the substrate, and a gate electrode on the gate dielectric layer.

20 more elements

A method to fabricate a drain extended transistor, the method comprising:

providing a semiconductor substrate, including:
a first side;
a second side spaced from the first side along a first direction;
and a first doped layer that includes majority carrier dopants of a first type;
forming an oxide structure along the first side of the semiconductor substrate;
providing a first mask along the first side of the semiconductor substrate to expose the oxide structure and a first portion of the first side of the semiconductor substrate;
performing a first implantation process that implants dopants of a second type into the semiconductor substrate at a first energy and a first dopant concentration using the first mask to form a first drift region portion that extends into the semiconductor substrate along the first direction from the first portion of the first side;
and
performing a second implantation process that implants dopants of the second type into the semiconductor substrate at a second energy and a second dopant concentration using the first mask to form a second drift region portion that extends into the semiconductor substrate under the oxide structure along the first direction, the second energy being greater than the first energy;
implanting dopants of the first type to form a body region having a channel portion adjacent the first drift region portion along a second direction;
forming a gate structure over the channel portion of the body region and over a portion of the oxide structure;
and
implanting dopants of the second type to form:
a source region adjacent the channel portion of the body region;
and a drain region adjacent the second drift region portion and the oxide structure.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/021,601Filed 28 Jun 2018
Published: 2 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 30/65
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets

Family

US 11,152,505 B2Related patent
US 2020/0006549 A1This patent

From the US filing history. Foreign family members aren’t listed.

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