Transistors with non-vertical gates

A method for fabricating a transistor device, the method comprising:

• providing a substrate;
• providing a buffer layer disposed on the substrate;
• providing a source disposed on the buffer layer;
• providing a drain disposed on the buffer layer;
• providing a channel disposed on the buffer layer;
• providing a sacrificial gate material and one or more spacers disposed on the channel;
• removing the sacrificial gate material and a portion of the buffer layer;
• removing a first portion of a first side of the channel to form a first recess having a first connecting portion proximate to the source and a second connecting portion proximate to the drain, wherein the first connecting portion or the second connecting portion comprises more than one angle;
• removing a second portion of a second side of the channel to form a second recess having a third connecting portion proximate to the source, and a fourth connecting portion proximate to the drain, wherein the third connecting portion or the fourth connecting portion comprises more than one angle;
• depositing a first gate material in the first recess;
• depositing a second gate material in the second recess;
• depositing a first gate on the first gate material;
• depositing a second gate on the second gate material;
• depositing a source contact on the source;
• and
• depositing a drain contact on the drain.

A method for fabricating a transistor device, the method comprising:

• providing a substrate;
• providing a buffer layer disposed on the substrate;
• providing a source disposed on the buffer layer, the source having a first crystallographic facet of a first orientation;
• providing a drain disposed on the buffer layer, the drain having a second crystallographic facet of a second orientation;
• providing a channel disposed on the buffer layer;
• providing a sacrificial gate material disposed on the channel;
• providing an interlayer dielectric layer disposed on the source and the drain;
• removing the sacrificial gate material to form a first recess and a portion of the buffer layer to form a second recess;
• removing a portion of the interlayer dielectric layer to form a third recess;
• depositing a first gate metal in the second recess;
• and
• depositing a second gate material and a second gate metal in the third recess.