Circuit and layout for resistive random-access memory arrays having two bit lines per column

A layout for a ReRAM memory array including rows and columns of ReRAM cells, each ReRAM cell in a row and column of ReRAM cells comprising:

• a ReRAM device;
• a first FinFET transistor coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell, the first FinFET transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell;
• a second FinFET transistor coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell, the second FinFET transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell;
• wherein each column includes a first group of fins and a second group of fins separate from the first group of fins;
• the first FinFET transistor for each memory cell in every column of the array is formed on the first group of fins associated with that column;
• and
• the second FinFET transistor for each memory cell in every column of the array is formed on the second group of fins associated with that column.