Reduction of metal resistance in vertical reram cells

A method for fabricating a vertical ReRAM array structure, the method comprising:

• forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, wherein the low resistivity material is a metal and forms a lateral electrode access layer;
• masking one or more portions of a topmost layer of the alternating layers;
• etching one or more portions of the alternating layers down to the metal layer;
• depositing a lateral electrode layer over the etched one or more portions of the alternating layers and the lateral electrode access layer;
• performing an etch back on the lateral electrode layer;
• and
• forming a vertical electrode layer over the structures, wherein the vertical electrode layer contacts the lateral electrode layer, wherein the lateral electrode layer contacts the lateral electrode access layer.