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US 2020/0006423 A1Published application
Processing and memory device and system
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Abstract
An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
Claims20
A device, comprising:
- an integrated circuit chip;
- at least one processing core integrated into the chip;
- and
- at least one magnetoresistive random access memory (MRAM) circuit integrated into the chip and communicatively coupled to the at least one processing core, the at least one MRAM circuit including a plurality of MRAM cells, wherein the at least one MRAM circuit, in operation, implements,
- at least one cache memory;
- and
- at least one main memory.
4 more elements
A system, comprising:
- an integrated circuit chip, the integrated circuit chip having:
- a processing core integrated into the chip;
- and
- magnetoresistive random access memory (MRAM) circuitry integrated into the chip, the MRAM circuitry including a plurality of MRAM cells organized into a plurality of MRAM memories, including at least one cache memory, and at least one main memory;
- a functional circuit;
- and
- a system bus, which, in operation, communicatively couples the functional circuit to the integrated circuit chip.
4 more elements
A method of manufacturing an integrated circuit, comprising:
- forming one or more processing cores of an integrated circuit chip in a substrate;
- and
- forming one or more magnetoresistive random access memory (MRAM) arrays of the integrated circuit chip in the substrate, the one or more MRAM arrays being organized into a plurality of memories including at least one cache memory and at least one main memory.
Dependencies are inferred from the claim text.