US 2020/0006379 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Claims20

Dependent claims

A semiconductor memory device comprising:

a first word line provided above a substrate;
a second word line provided above the first word line;
a third word line provided above the second word line;
a first semiconductor layer including a first part that passes through the first word line, and is provided above the substrate, a second part that passes through the second and the third word lines, and is provided above the first part, and a first joint that is provided between the first part and the second part;
a first bit line electrically connected to the first semiconductor layer;
and
a row decoder that applies a voltage to the first, the second, and the third word lines, wherein
when a write operation is performed on a memory cell transistor connected to the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to the first bit line, a second voltage is applied to the third word line, and a third voltage that is higher than the second voltage is applied to the second word line.

5 more elements

A semiconductor memory device comprising:

conductive layers stacked above a substrate via insulation layers;
a first memory pillar including a first column above the substrate, a second column above the first column, and a first joint between the first column and the second column, and that passes through the conductive layers;
a first wiring layer electrically connected to the first memory pillar;
a row decoder that applies a voltage to the conductive layers;
and
a sense amplifier that applies a voltage to the first wiring layer, wherein
the conductive layers include a first conductive layer that is above the first joint, and a second conductive layer that is distant from the first joint than the first conductive layer, and is adjacent to the first conductive layer,
in a write operation with respect to the second conductive layer, the write operation includes a pre-charge period, and a program period after the pre-charge period,
in the pre-charge period, the sense amplifier applies a first voltage to the first wiring layer, and the row decoder applies a second voltage to the second conductive layer, and applies a third voltage that is higher than the second voltage to the first conductive layer, and
in the program period, the row decoder applies a write voltage to the second conductive layer.

7 more elements

A semiconductor memory device comprising:

conductive layers stacked above a substrate via insulation layers;
a memory pillar including a first pillar above the substrate, a second pillar above the first pillar, and a joint between the first pillar and the second pillar, and that passes through the conductive layers;
a wiring layer electrically connected to the memory pillar;
a row decoder that applies a voltage to the conductive layers;
and
a sense amplifier that applies a voltage to the wiring layer, wherein
the conductive layers include a first conductive layer that is provided above the joint, a second conductive layer that is more distant from the joint than the first conductive layer, and is adjacent to the first conductive layer, a third conductive layer that is provided above the joint, and is adjacent to the joint, and a fourth conductive layer that is provided below the joint, and is adjacent to the joint, wherein
an interval between the third conductive layer and the fourth conductive layer is wider than an interval between the second conductive layer and the first conductive layer,
in a write operation with respect to the second conductive layer, the write operation includes a pre-charge period, and a program period after the pre-charge period,
in the pre-charge period, the sense amplifier applies a first voltage to the wiring layer, and the row decoder applies a second voltage to the second conductive layer, and applies a third voltage that is higher than the second voltage to the first conductive layer, and
in the program period, the row decoder applies a write voltage to the second conductive layer.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20