US 2020/0006340 A1 · PEDESTAL FIN STRUCTURE FOR STACKED TRANSISTOR INTEGRATION

Abstract

Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

Claims20

Dependent claims

An integrated circuit structure, comprising:

a body comprising one or more semiconductor materials and having a first width defined by a distance between opposing sidewalls of the body;
a first transistor above the body and including a first fin, nanowire, or nanoribbon, the first fin, nanowire, or nanoribbon having a second width defined by a distance between opposing sidewalls of the first fin, nanowire, or nanoribbon;
and
a second transistor below the body and including a second fin, nanowire, or nanoribbon, the second fin, nanowire, or nanoribbon having a third width defined by a distance between opposing sidewalls of the second fin, nanowire, or nanoribbon;
wherein one or both of the second and third widths is at least 1.5 times less than the first width.

2 more elements

An integrated circuit structure, comprising:

a body comprising one or more semiconductor materials and having a first width defined by a distance between opposing sidewalls of the body;
a first transistor structure above the body and including a first plurality of fins, nanowires, or nanoribbons, the first transistor structure including a first gate structure, a first source region, and a first drain region;
and
a second transistor structure below the body and including a second plurality of fins, nanowires, or nanoribbons, the second transistor structure including a second gate structure, a second source region, and a second drain region;
wherein one or more of the fins, nanowires, or nanoribbons of the first plurality has a second width, and one or more of the fins, nanowires, or nanoribbons of the second plurality has a third width, one or both of the second and third widths being at least 1.5 times less than the first width;
and
wherein the opposing sidewalls of the body are collinear with an outermost sidewall included in the first plurality of fins, nanowires, or nanoribbons and/or an outermost sidewall included in the second plurality of fins, nanowires, or nanoribbons.

4 more elements

Dependencies are inferred from the claim text.

Pedestal fin structure for stacked transistor integration

Life of this patent

Pedestal fin structure for stacked transistor integration

Life of this patent

Abstract

Claims20