Stress Reduction Apparatus and Method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYao-Chun Chuang, Yu-Chen Hsu, Haochun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYao-Chun Chuang, Yu-Chen Hsu, Haochun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
Estimating the term…
A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
A method comprising:
A method comprising:
A method comprising:
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