Method and Apparatus for Back End of Line Semiconductor Device Processing

A method of fabricating an integrated circuit (IC), the method comprising:

• forming a first metal feature in a first dielectric layer, the first metal feature protruding through an upper surface of the first dielectric layer;
• forming an etch stop layer over the first metal feature, the etch stop layer extending over the first metal feature;
• forming a second dielectric layer over the etch stop layer;
• forming a recess in the second dielectric layer and the etch stop layer, the first metal feature protruding above a bottom surface of the recess;
• and
• forming a second metal feature in the recess.

A method of fabricating an integrated circuit (IC), the method comprising:

• forming a first dielectric layer;
• forming a first metal feature in the first dielectric layer;
• recessing the first dielectric layer, the first metal feature protruding above an upper surface of the first dielectric layer after recessing;
• forming an etch stop layer over the first dielectric layer, the etch stop layer covering the first metal feature;
• forming a second dielectric layer over the etch stop layer;
• forming a recess in the second dielectric layer and the etch stop layer, the recess extending only partially through the etch stop layer, the first metal feature extending above a bottom of the recess;
• and
• forming a second metal feature in the recess.