US 2020/0005880 A1 · PROGRAM PROGESS MONITORING IN A MEMORY ARRAY

Abstract

A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.

Claims25

Dependent claims

A memory device comprising:

a memory array including multi-level memory cells;
buffer circuitry;
a memory control unit operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels including a first programming level, one or more intermediate programming levels, and a final programming level;
a program progress indicator including a program progress register to store a value updated by the memory control unit to indicate completion of each programming level as the programming of the multiple programming levels progresses including the first programming level and the one or more intermediate programming levels;
and
wherein the memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of a programming level by the program progress indicator.

3 more elements

A method of programming multi-level memory cells of a memory array, the method comprising:

loading first data into a page buffer;
programming the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels;
updating a value of a program progress indicator in response to completion of programming of each programming level of the multiple programming levels including the first programming level and the one or more intermediate programming levels;
and
loading second data into the page buffer for programming of the multi-level memory cells according to the value of the program progress indicator.

2 more elements

A non-transitory computer readable storage medium comprising instructions configured to cause a memory control unit of a memory device to:

load first data into a page buffer for programming of the multi-level memory cells;
initiate multiple programming passes that program the multi-level memory cells;
update a value of a program progress indicator to indicate completion of programming passes and completion of programming of each level of the multiple-level memory cells including a first programming level, one or more intermediate programming levels, and a final programming level;
and
load second data into the page buffer for programming of the multi-level memory cells according to the value of a program progress indicator.

2 more elements

Dependencies are inferred from the claim text.

Program progess monitoring in a memory array

Life of this patent

Program progess monitoring in a memory array

Life of this patent

Abstract

Claims25