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US 2020/0005848 A1Published application
Symmetrically programmable resistive synapse for rpu using current-programmed single domain wall ferroelectric
AssigneeInternational Business Machines Corporation
InventorsMartin M. Frank, Jin-Ping Han, Dennis M. Newns, Paul M. Solomon, Xiao Sun
Life of this patent
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Abstract
A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
Claims20
A circuit comprising:
- a ferroelectric tunneling junction (“FTJ”) with a first side coupled in series with a YR read line;
- a pull-up circuit having a write line YW as a first input with an output in series with a second side of the FTJ;
- and
- a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
1 more element
A method of operating an FTJ, the method comprising:
- receiving, using a memory controller, a command;
- determining, using a memory controller, that the command is a write up command, a write down command, or a read command;
- based at least in part on the command being a write up command and YN being equal to zero, removing, using a memory controller, charge from the FTJ with a substantially constant current removed over a period of time;
- and
- based at least in part on the command being a write down command and YN being equal to one, adding, using a memory controller, charge to the FTJ with a substantially constant current added over a period of time.
2 more elements
A circuit comprising:
- a YW line;
- a first analog inverter with its input coupled to the YW line;
- a second analog inverter with its input coupled to the YW line;
- a PFET with its gate coupled to the output of the first inverter and its source coupled to VDD;
- an NFET with its gate coupled to the output of the second inverter and its source coupled to ground;
- an FTJ with a first side coupled to the drain of the PFET and the drain of the NFET and a second side coupled to a YR line;
- and
- a second NFET with its gate coupled to an RE line, its drain coupled to the first side of the FTJ, and its source coupled to an XR line.
5 more elements
Dependencies are inferred from the claim text.