Compact magnetic storage memory cell
AssigneesCommissariat à I'Énergie Atomique et aux Énergies Alternatives, Centre National De La Recherche Scientifique
InventorsRana Alhalabi, Grégory Di Pendina
Life of this patent
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Abstract
A memory comprising an array of memory cells, each memory cell comprising: first and second resistive storage elements each having at least first and second terminals; and a first transistor having: a first main conducting node connected to the first terminal of the first resistive element and to a first column/row line of the array; and a second main conducting node connected to the first terminal of the second resistive element and to a second column/row line of the array.
Claims13
A memory comprising an array of memory cells, each memory cell comprising:
- first and second resistive storage elements each having at least first and second terminals;
- and
- a first transistor having:
- a first main conducting node connected to the first terminal of the first resistive element and to a first column/row line of the array;
- and
- a second main conducting node connected to the first terminal of the second resistive element and to a second column/row line of the array;
- and
- a switch circuit comprising:
- a first switch configured to be capable of coupling together the first and second terminals of the first resistive storage element of each memory cell of a first row or column of the array;
- and
- a second switch configured to be capable of coupling together the first and second terminals of the second resistive storage element of each memory cell of the first row or column of the array.
A method of accessing a memory cell of an array, each memory cell having first and second resistive storage elements each having first and second terminals, and a first transistor coupling together first terminals of the first and second resistive storage elements, the method comprising:
- bypassing, using a switch circuit, one of the first and second resistive storage elements via column/row lines of the memory array in order to access the other of the first and second resistive storage elements, the switch circuit comprising:
- a first switch configured to be capable of coupling together the first and second terminals of the first resistive storage element of each memory cell of a first row or column of the array;
- and
- a second switch configured to be capable of coupling together the first and second terminals of the second resistive storage element of each memory cell of the first row or column of the array.
Dependencies are inferred from the claim text.