Memory device with dynamic processing level calibration

A method of operating a system including a processing device and a memory array, the method comprising iteratively:

• determining a first error rate based on using an active processing level;
• determining a second error rate based on using an offset processing level instead of the active processing level to process data corresponding to at least a portion of the plurality of memory cells;
• and
• incrementally adjust the current processing level based on a comparison of the first error rate and the second error rate for each iteration.

A system, comprising:

• a memory array including non-volatile memory cells arranged in memory pages;
• and
• a processing device coupled to the memory array, the processing device configured to iteratively adjust a current read level voltage used to read stored data, wherein, for each iteration, the processing device is configured to:
• determine a first error count corresponding to the active read level voltage,
• determine a second error count based on using an offset read level voltage instead of the active read level voltage, and
• incrementally adjust the active read level voltage for the memory page based on a comparison of the first error count and the second error count for each iteration.