Combining load or store instructions

An apparatus, comprising:

• means for identifying, in a processor pipeline, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width;
• means for determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line;
• and
• means for replacing, within the processor pipeline, the multiple memory access instructions with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

A computer-readable medium having computer-executable instructions recorded thereon, the computer-executable instructions configured to cause a processor to:

• identify, in a pipeline associated with the processor, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width;
• determine that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line;
• and
• replace, within the pipeline associated with the processor, the multiple memory access instructions with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.