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US 2020/0004548 A1Published application
Shared local memory tiling mechanism
AssigneeIntel Corporation
InventorsPrasoonkumar Surti, Abhishek R. Appu, Joydeep Ray, Subramaniam M. Maiyuran, Altug Koker
Life of this patent
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Abstract
An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.
Claims21
1-19. (canceled)
An apparatus comprising:
- a shared local memory;
- and
- one or more processors including a plurality of streaming multiprocessors (SMs) to execute a plurality of thread groups via access to the shared local memory, each thread group of the plurality of thread groups including a plurality of processing threads;
- and
- wherein the one or more processors are to:
- detect access patterns and data layout properties for each thread group,
- generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group, and
- apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory.
5 more elements
A graphics processing system comprising:
- a shared local memory;
- and
- a graphics processor including a plurality of streaming multiprocessors (SMs) to execute a plurality of thread groups via access to the shared local memory, each thread group of the plurality of thread groups including a plurality of processing threads;
- and
- wherein the graphics processor is to:
- detect access patterns and data layout properties for each thread group,
- generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group, and apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory.
4 more elements
A method comprising:
- detecting access patterns and data layout properties to a shared local memory for a plurality of thread groups executed at a plurality of streaming multiprocessors (SMs) of one or more processors, each thread group of the plurality of thread groups including a plurality of processing threads;
- generating a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group;
- and
- applying the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory.
1 more element
A non-transitory computer readable medium having instructions, which when executed by one or more processors, cause the processors to:
- detect access patterns and data layout properties to a shared local memory for a plurality of thread groups executed at a plurality of streaming multiprocessors (SMs) of one or more processors, each thread group of the plurality of thread groups including a plurality of processing threads;
- generate a tiling pattern for each thread group based at least in part on the detected access patterns and data layout properties for the thread group;
- and
- apply the generated tiling pattern for each thread group to memory addresses for data stored in the shared local memory.
1 more element
Dependencies are inferred from the claim text.