Prefetcher for delinquent irregular loads

A processor comprising:

• a cache memory;
• fetch and decode circuitry to fetch and decode instructions from a memory;
• and
• a binary translator (BT) to respond to the decoded instructions by:
• storing a plurality of the decoded instructions in a BT cache;
• identifying a delinquent irregular load (DIRRL) among the stored instructions;
• determining whether the DIRRL is prefetchable;
• and
• if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

A non-transitory computer-readable medium containing instructions that, when performed by a computing apparatus, cause the computing apparatus to respond by:

• fetching and decoding instructions from a memory using fetch and decode circuitry;
• and
• responding to decoded instructions using a binary translator (BT) to:
• store a plurality of decoded instructions in a BT cache memory;
• track cache misses of load instructions to identify delinquent loads;
• profile address deltas of successive instances of the delinquent loads to identify a delinquent irregular load (DIRRL);
• and
• determine, by analyzing a backslice between successive dynamic instances of the DIRRL, whether the DIRRL is prefetchable, and, if so, generate a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.