Multi-level cell data load optimization

A memory circuit including:

• memory cells configured to provide multi-level cell (MLC) storage;
• and
• a controller operably coupled to the memory cells, the controller configured to perform operations, comprising:
• receiving an indication of a production mode of a device including the memory circuit;
• receiving an estimated size of a subsequent download during the production mode, to configure at least a portion of the memory cells from operation as MLC storage to operation as single-level cell (SLC) storage in response to the estimated size;
• receiving a direct the subsequent download to the memory cells, and
• upon receiving an indication that the device is leaving the production mode, reconfiguring the at least portion of the memory cells from operation as SLC storage to operation as MLC storage, simultaneously maintaining, within the memory cell, information included as part of the subsequent download.

A machine-readable medium, comprising instructions, which when executed by a machine, cause the machine to perform operations comprising:

• receiving a first indication indicative of a production mode of an apparatus including a memory device;
• receiving first information indicative of a subsequent download of second information at the memory device, the memory device including a first group of cells configured to operate as multi-level cell (MLC) memory;
• in response to receipt of the first information, converting a portion of the first group of cells from operation as MLC memory to operation as single-level cell (SLC) memory;
• receiving and storing the second information at the memory device;
• and
• upon exiting the first mode of operation, reconfiguring at least a portion of the SLC memory to operate as MLC memory while simultaneously maintaining storage of the second information within the memory device.