US 2020/0004289 A1 · DATA STROBE MULTIPLEXER

Abstract

Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Claims20

Dependent claims

A system comprising:

a host device;
and
a multiplexer circuit configured to receive a data signal and a data strobe signal from an embedded MultiMediaCard (eMMC) device, and to selectively provide one of the data signal or the data strobe signal to a data pin of the host device,
wherein the host device is configured to receive an output of the multiplexer circuit at a data pin of the host device, and to determine a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin and an internal clock signal.

1 more element

A method comprising:

receiving a data signal and a data strobe signal at a host device from an embedded MultiMediaCard (eMMC) device at a multiplexer circuit;
selectively providing, using the multiplexer circuit, one of the data signal or the data strobe signal to a data pin of the host device;
receiving an output of the multiplexer circuit at a data pin of the host device;
and
determining, using the host device, a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin and an internal clock signal to control a delay circuit of the host device.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/022,307Filed 28 Jun 2018

Published

2 Jan 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 13/1689
Details of memory controller: synchronisation and timing concerns
G06F 13/4243
Being a memory bus: with synchronous protocol
G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…

Data strobe multiplexer

Life of this patent

Data strobe multiplexer

Life of this patent

Abstract

Claims20