Mask making method

A method of calibrating a lithography model, the method comprising:

• computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing the TCC matrix includes decomposing the TCC matrix into a single ideal TCC kernel set for a corresponding ideal optical system and at least two perturbation kernel sets, wherein coefficients of the at least two perturbation kernel sets correspond to optical defects in the optical system;
• calibrating a lithography model includes iteratively adjusting the lithography model by comparing simulated wafer patterns to measurements of printed wafer patterns;
• providing the calibrated lithography model including the calibrated ideal TCC kernel set and the calibrated at least two perturbation kernels sets and a resist model to obtain a synthesized mask layout corresponding to a target mask layout;
• and
• printing a wafer using a mask obtained from the synthesized mask layout.

A tool for making a lithography mask, the tool comprising:

• a processor;
• and
• a memory operably connected to the processor, and having a computer-executable instructions stored thereon, the instructions when executed cause the processor to:
• receive a mask layout;
• compute a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the TCC matrix into an ideal TCC kernel set for a corresponding ideal optical system and at least two perturbation kernels sets having coefficients corresponding to optical defects in the optical system;
• calibrate a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns;
• and
• provide the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the lithography mask using the synthesized mask layout, wherein
• the printed wafer patterns are obtained using a test mask that is fabricated using a test mask layout, and
• the simulated wafer patterns are obtained by applying a lithography model including an ideal TCC kernel set, at least two perturbation kernels sets, and a resist model to the test mask layout.