Cmos image sensor systems using low-power multi-mode data path and methods of processing the same

A complementary metal-oxide semiconductor (CMOS) Image Sensor (CIS) system, comprising:

• a pixel array for outputting pixel data of mergeable 4-shared pixel arrays with arrangement of a plurality of pixels;
• a data arrangement unit having a single data arrangement module to correspond to each of the 4-shared pixel arrays and for merging pixel data of the same color in another row of the 4-shared pixel arrays to rearrange data in a low power mode;
• a data reading unit for performing an exclusive-OR operation of data output from the data arrangement unit to discharge and pre-charge the data when an input voltage of a sense line pull-down circuit is equal to or higher than a high level;
• and
• a data transmitting unit for dividing and transmitting data of the most significant bit (MSB) side and data of the Least Significant Bit (LSB) side of data having the same color among data read by the data reading unit.