Digital Oversampling Clock And Data Recovery Circuit

An apparatus comprising:

• an analog front end to receive a digital input, the analog front end to output a data stream from the digital input;
• a data sampler to output recovered data from the data stream based on a recovery clock signal;
• a first time-to-digital converter (TDC) comprising a first counter to count a first count value corresponding to a first duration of a sample of the data stream, wherein the first counter is to be asynchronously reset responsive detection of a first edge in the data stream;
• a second TDC comprising a second counter to count a second count value corresponding to a second duration of another sample of the data stream, wherein the second counter is to be asynchronously reset responsive to detection of a second edge in the data stream;
• a math processing unit to filter a count value obtained based at least in part on the first count value and the second count value;
• and
• a digitally controlled oscillator to generate the recovery clock signal from the filtered count value.

A mobile device comprising:

• a processor;
• a non-volatile memory coupled to the processor;
• and
• an interface circuit coupled to the processor, the interface circuit comprising a clock and data recovery (CDR) circuit comprising:
• an analog front end to receive a digital input and output a data stream therefrom;
• a data sampler to output recovered data from the data stream based on a recovery clock signal;
• a first time-to-digital converter (TDC) comprising a first counter to count a first count value corresponding to a first duration of a sample of the data stream, wherein the first counter is to be asynchronously reset responsive detection of a first edge in the data stream;
• a second TDC comprising a second counter to count a second count value corresponding to a second duration of another sample of the data stream, wherein the second counter is to be asynchronously reset responsive to detection of a second edge in the data stream;
• and
• a digitally controlled oscillator to generate the recovery clock signal based at least in part on the first count value and the second count value.