Architecture for high-speed computation of error-detecting crc codes of data packets transferred via directly connected bus

Architecture for High-speed Computation of Error-detecting CRC Codes of Data Packets Transferred via Directly Connected Bus characterized by the fact that firstly the data bus is by its data outputs interconnected with N parallel submodules (9 or 19) specialized to compute CRC values from given parts of data bus word (9.1 or 19.1), the number of which (N) is given by the maximal number of data packets transferred in a single data bus word;

• secondly the unique form of intermediate CRC values distribution is realized between submodules (9) through signals (9.2, 9.4) and register (10) in serial version of top-level architecture or between submodules (19) through signals (19.2, 19.4, 19.5, 19.6) and register (20) in parallel version of the top-level architecture, where the internal structure of individual submodules (9 or 19) is specifically tailored for such an arrangement;
• and finally the structure of each submodule (9 or 19) capable of processing one part of data bus word separates the main CRC value computation without any regard to packet boundaries (4) from the specific alterations of this process required to correctly handle continuing, starting or ending data packets, which is realized independently mainly by component (1) connected to data and control signals of the input data bus (1.1, 1.2, 1.3) for handling packet starts, component (8) connected to masked data signal (3.1) and intermediate CRC values (7.2) through multiplexers (3, 7) controlled by output (2.2) of component (2) for handling packet ends, and by component (6) together with multiplexers (5) handling the correct aggregation and distribution of intermediate CRC values (4.1, 5.1, 5.4, 6.1) for each submodule (9 or 19);
• where such parallel arrangement of submodules enables finalization of independent CRC values (9.3 or 19.3) for multiple (up to N) data packets that are simultaneously ending in the same single word of the connected data bus.