Voltage-controlled oscillators with ramped voltages

A phase locked loop (PLL) system, comprising:

• a phase-frequency detector (PFD);
• a charge pump coupled to the PFD;
• first and second comparators, each of the first and second comparators having inputs coupled to an output of the charge pump and configured to receive first and second reference voltages, respectively;
• a digital controller coupled to outputs of the first and second comparators;
• and
• a voltage-controlled oscillator (VCO) coupled to the output of the charge pump, the VCO including:
• an inductor;
• a first pair of transistors coupled to a voltage source and to the inductor;
• a second pair of transistors coupled to ground and to the inductor;
• a first transistor coupled to a capacitor, the combination of the first transistor and the capacitor coupled in parallel with the inductor, the first transistor having a control terminal;
• second, third, and fourth transistors coupled to the control terminal of the first transistor, the second and fourth transistors coupled to the voltage source and to ground, respectively, and the third transistor coupled to an output of the digital controller, the second, third, and fourth transistors also coupled to outputs of the digital controller;
• and
• a coarse capacitor bank coupled to the inductor in parallel.

A method comprising:

• operating a phase locked loop (PLL) voltage-controlled oscillator (VCO);
• detecting that a voltage output by a charge pump of the PLL exceeds a voltage threshold;
• and
• in response to the detection:
• turning on a first transistor;
• turning off a second transistor after turning on the first transistor;
• applying a ramped voltage to the first transistor after turning off the second transistor, wherein applying the ramped voltage to the first transistor causes a capacitance of the VCO to change;
• turning on a third transistor;
• and
• turning off the first transistor after turning on the third transistor.