On-Die Termination
AssigneeRambus Inc.
InventorIan Shaeffer
Life of this patent
Estimating the term…
Abstract
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
Claims22
(canceled)
An integrated circuit (IC) package comprising:
- a segment of a signaling link to communicate first data and second data;
- a first memory device having:
- a first data node coupled to the segment of the signaling link to communicate the first data;
- a first termination circuit coupled to the first data node to apply a first impedance to the segment of the signaling link;
- a first termination-control register coupled to the first termination circuit to select the first impedance;
- and
- a first peer-control node to transmit a peer-control signal;
- and
- a second memory device having:
- a second data node coupled to the segment of the signaling link to communicate the second data;
- a second termination circuit coupled to the second data node to apply a second impedance to the segment of the signaling link while the first memory device communicates the first data over the first data node;
- a second termination-control register coupled to the second termination circuit to select the second impedance;
- and
- a second peer-control node coupled to the first peer-control node to receive the peer-control signal.
A method of operation in data termination for a plurality of memory devices of an IC package communicating data on a segment of a signaling link, the memory devices including a first memory device having a first data node coupled to the segment of the signaling link and a second memory device having a second data node coupled to the segment of the signaling link, the method comprising:
- receiving a first termination-control value;
- storing the first termination-control value in a first termination-control register on the first memory device, the first termination-control value setting a first termination impedance to the segment of the signaling link;
- passing a peer-control signal from the first memory device to the second memory device;
- receiving a second termination-control value;
- storing the second termination-control value in a second termination-control register on the second memory device, the second termination-control value setting a second termination impedance to the segment of the signaling link;
- receiving first write data, directed to the first memory device, on the segment of the signaling link;
- and
- while receiving the first write data, applying the second termination impedance to terminate the segment of the signaling link.
A memory device comprising:
- a data node for communicating first data over a data link;
- a termination circuit coupled to the data node to terminate the data link, the termination circuit supporting an off state and a first termination impedance;
- a termination-control register coupled to the termination circuit, the termination- control register to store a value selecting one of the off state and the termination impedance;
- and
- a peer-control node to issue a peer-control signal to a peer device, the peer device to:
- communicate second data over the data link;
- and
- apply a second termination impedance to the data link when the memory device communicates the first data over the data link with the termination circuit in the off state.
Dependencies are inferred from the claim text.