Asymmetric pulse width comparator circuit and clock phase correction circuit including the same

An asymmetric pulse width comparison circuit, comprising:

• a first capacitor set which is discharged during an activation period of a first pulse signal after being charged to a logic high level and has a first capacitance value;
• a second capacitor set which is discharged during an activation period of a second pulse signal after being charged to a logic high level, and has a second capacitance value, which is N times the first capacitance value, where N is a real number greater than 1;
• and
• a comparator suitable for comparing a voltage level of the first capacitor set with a voltage level of the second capacitor set.

An asymmetric pulse width comparison circuit, comprising:

• a first capacitor set which is charged during an activation period of a first pulse signal after being discharged to a logic low level and has a first capacitance value;
• a second capacitor set which is charged during an activation period of a second pulse signal after being discharged to a logic low level, and has a second capacitance value, which is N times the first capacitance value, where N is a real number greater than 1;
• and
• a comparator suitable for comparing a voltage level of the first capacitor set with a voltage level of the second capacitor set.

A clock phase correction circuit comprising:

• a plurality of delay circuits suitable for receiving source clocks, delaying the source clocks based on delay codes and generating multi-phase clocks including a reference clock and other clocks, each of the other clocks having a set phase difference with the reference clock;
• and
• a plurality of phase difference detection circuits, wherein each of the phase difference detection circuits:
• receives the reference clock and a corresponding one of the other clocks,
• detects a phase difference between the reference clock and the corresponding other clock, and
• generates a corresponding delay code based on the detected phase difference such that the detected phased difference is the same as the set phase difference for the corresponding other clock.