Driving circuit for power switch

A driving circuit for driving a power switch comprising an input capacitor, the driving circuit comprising:

• an inductor;
• a resistor comprising a parasitic resistor of the driving circuit;
• and
• a first driving switch and a second driving switch electrically connected with the inductor, wherein the first driving switch and the second driving switch are electrically connected with each other and electrically connected with the inductor, wherein the first driving switch comprises a first parasitic capacitor and the second driving switch comprises a second parasitic capacitor,
• wherein the driving circuit is configured such that a first equivalent capacitor is formed corresponding to the input capacitor, and a second equivalent capacitor is formed corresponding to one or both of the first and second parasitic capacitors,
• wherein the first equivalent capacitor, the inductor, the resistor and the second equivalent capacitor are serially connected with each other to form an equivalent circuit to discharge the input capacitor of the power switch, and a discharging procedure of the input capacitor is performed through the equivalent circuit,
• wherein during the discharging procedure, firstly, the first driving switch and the second driving switch are turned on by turns, which causes the voltage of the input capacitor to decrease to a minimum voltage Vp2, and there is substantially no inductor current when the voltage of the input capacitor is at the minimum voltage Vp2, then, the first driving switch and the second driving switch are turned off, which causes the voltage of the input capacitor to increase from the minimum voltage Vp2 to a second steady voltage,
• wherein the first and second equivalent capacitors are configured such that:
• (1) during the discharging procedure, while the voltage of the input capacitor is changed from the minimum voltage Vp2 to the second steady voltage, a third amount of charges discharged from the input capacitor is equal to Q3, whereas while the voltage of the input capacitor is changed from the minimum voltage Vp2 to a second set voltage VL a fourth amount of charges discharged from the input capacitor is equal to Q4, wherein Q4 is greater than or equal to Q3, and
• (2) the second steady voltage is lower than the second set voltage VL, and the second set voltage VL is lower than a minimum threshold Vmin of the gate terminal of the power switch.