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US 2019/0379361 A1Published application
Flip-flop
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-Chul HWANG, Min-Su Kim, Dae-Seong Lee
Life of this patent
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Abstract
A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.
Claims11
(canceled)
A flip-flop comprising:
- a first OR-gate element including a first input terminal configured to receive a clock signal, a second input terminal configured to receive input data, and an output terminal configured to output an OR-operation result between the clock signal and the input data;
- a first NAND-gate element including a first input terminal connected to the output terminal of the first OR-gate element, a second input terminal connected to a second node, and an output terminal connected to a first node, said output terminal of said first NAND-gate element being configured to output a NAND-operation result between the OR-operation result of the first OR-gate element and a voltage signal of the second node at the first node;
- a second OR-gate element including a first input terminal configured to receive inverted input data, a second input terminal configured to receive the clock signal, and an output terminal configured to output an OR-operation result between the inverted input data and the clock signal;
- a second NAND-gate element including a first input terminal connected to the first node, a second input terminal connected to the output terminal of the second OR-gate element, and an output terminal connected to the second node, said output terminal of the second NAND-gate element being configured to output a NAND-operation result between a voltage signal of the first node and the OR-operation result of the second OR-gate element at the second node;
- a first inverter element connected between the second input terminal of the first OR-gate element and the first input terminal of the second OR-gate element, said first inverter element being configured to invert the input data and to output the inverted input data;
- a third AND-gate element including a first input terminal connected to the first node, a second input terminal configured to receive the clock signal, and an output terminal configured to output an AND-operation result between the clock signal and the voltage signal of the first node;
- a first NOR-gate element including a first input terminal connected to the output terminal of the third AND-gate element, a second input terminal connected to a sixth node, and an output terminal connected to a fifth node, said output terminal of the first NOR-gate element being configured to output a NOR-operation result between the AND-operation result of the third AND-gate element and a voltage signal of the sixth node at the fifth node;
- a fourth AND-gate element including a first input terminal connected to the second node, a second input terminal configured to receive the clock signal, and an output terminal configured to output an AND-operation result between the voltage signal of the second node and the clock signal;
- and
- a second NOR-gate element including a first input terminal connected to the fifth node, a second input terminal connected to the output terminal of the fourth AND-gate element, and an output terminal connected to the sixth node, said output terminal of the second NOR-gate element being configured to output a NOR-operation result between a voltage signal of the fifth node and the AND-operation result of the fourth AND-gate element at the sixth node.
7 more elements
A flip-flop comprising:
- a first AND-gate element including a first input terminal connected to a second node, a second input terminal configured to receive a clock signal, a third input terminal connected to a fifth node, and an output terminal configured to output an AND-operation result among a voltage signal of the second node, the clock signal, and a voltage signal of the fifth node;
- a first OR-gate element including a first input terminal connected to the output terminal of the first AND-gate element, a second input terminal configured to receive input data, and an output terminal configured to output an OR-operation result between the AND-operation result of the first AND-gate element and the input data;
- a first NAND-gate element including a first input terminal connected to the output terminal of the first OR-gate element, a second input terminal connected to the second node, and an output terminal connected to a first node, said output terminal of the first NAND-gate element being configured to output a NAND-operation result between the OR-operation result of the first OR-gate element and the voltage signal of the second node at the first node;
- a second AND-gate element including a first input terminal connected to the first node, a second input terminal configured to receive the clock signal, a third input terminal connected to a sixth node, and an output terminal configured to output an AND-operation result among a voltage signal of the first node, the clock signal, and a voltage signal of the sixth node;
- a second OR-gate element including a first input terminal configured to receive inverted input data, a second input terminal connected to the output terminal of the second AND-gate element, and an output terminal configured to output an OR-operation result between the inverted input data and the AND-operation result of the second AND-gate element;
- a second NAND-gate element including a first input terminal connected to the first node, a second input terminal connected to the output terminal of the second OR-gate element, and an output terminal connected to the second node, said output terminal of the second NAND-gate element being configured to output a NAND-operation result between the voltage signal of the first node and the OR-operation result of the second OR-gate element at the second node;
- a first inverter element connected between the second input terminal of the first OR-gate element and the first input terminal of the second OR-gate element, said first inverter element being configured to invert the input data and to output the inverted input data;
- a third OR-gate element including a first input terminal configured to receive the inverted input data, a second input terminal connected to the first node, and an output terminal configured to output an OR-operation result between the inverted input data and the voltage signal of the first node;
- a third AND-gate element including a first input terminal connected to the output terminal of the third OR-gate element, a second input terminal configured to receive the clock signal, a third input terminal that is connected to the first node, and an output terminal configured to output an AND-operation result among the OR-operation result of the third OR-gate element, the clock signal and the voltage signal of the first node;
- a first NOR-gate element including a first input terminal connected to the output terminal of the third AND-gate element, a second input terminal connected to the sixth node, and an output terminal connected to the fifth node, said output terminal of the first NOR-gate element being configured to output a NOR-operation result between the AND-operation result of the third AND-gate element and the voltage signal of the sixth node at the fifth node;
- a fourth OR-gate element including a first input terminal connected to the second node, a second input terminal configured to receive the input data, and an output terminal configured to output an OR-operation result between the voltage signal of the second node and the input data;
- a fourth AND-gate element including a first input terminal connected to the second node, a second input terminal configured to receive the clock signal, a third input terminal connected to the output terminal of the fourth OR-gate element, and an output terminal configured to output an AND-operation result among the voltage signal of the second node, the clock signal, and the OR-operation result of the fourth OR-gate element;
- and
- a second NOR-gate element including a first input terminal connected to the fifth node, a second input terminal connected to the output terminal of the fourth AND-gate element, and an output terminal connected to the sixth node, said output terminal of the second NOR-gate element being configured to output a NOR-operation result between the voltage signal of the fifth node and the AND-operation result of the fourth AND-gate element at the sixth node.
11 more elements
A flip-flop comprising:
- a first p-channel metal oxide semiconductor (PMOS) transistor including a first terminal connected to a high power voltage, a second terminal, and a gate terminal configured to receive a clock signal;
- a second PMOS transistor including a first terminal connected to the high power voltage, a second terminal connected to the second terminal of the first PMOS transistor, and a gate terminal connected to a second node;
- a fourteenth PMOS transistor including a first terminal connected to the second terminal of the first PMOS transistor, a second terminal connected to a third node, and a gate terminal configured to receive a set signal;
- a third PMOS transistor including a first terminal connected to the third node, a second terminal connected to a first node, and a gate terminal configured to receive input data;
- a first n-channel metal oxide semiconductor (NMOS) transistor including a first terminal connected to the first node, a second terminal, and a gate terminal;
- a second NMOS transistor including a first terminal connected to the second terminal of the first NMOS transistor, a second terminal connected to a low power voltage, and a gate terminal;
- a fourteenth NMOS transistor including a first terminal connected to the first node, a second terminal connected to the low power voltage, and a gate terminal configured to receive the set signal;
- a fifteenth PMOS transistor including a first terminal connected to the high power voltage, a second terminal, and a gate terminal configured to receive the set signal;
- a fourth PMOS transistor including a first terminal connected to the second terminal of the fifteenth PMOS transistor, a second terminal connected to the first node, and a gate terminal connected to the second node;
- a third NMOS transistor including a first terminal connected to the first node, a second node, and a gate terminal connected to the second node;
- a fifth PMOS transistor including a first terminal connected to the high power voltage, a second terminal connected to a fourth node, and a gate terminal configured to receive the clock signal;
- a sixth PMOS transistor including a first terminal connected to the high power voltage, a second terminal connected to the fourth node, and a gate terminal connected to the first node;
- a seventh PMOS transistor including a first terminal connected to the fourth node, a second terminal connected to the second node, and a gate terminal configured to receive inverted input data;
- a fourth NMOS transistor including a first terminal connected to the second node, a second terminal, and a gate terminal;
- a fifth NMOS transistor including a first terminal connected to the second terminal of the fourth NMOS transistor, a second terminal connected to the low power voltage, and a gate terminal;
- an eighth PMOS transistor including a first terminal connected to the high power voltage, a second terminal connected to the second node, and a gate terminal connected to the first node;
- a sixth NMOS transistor including a first terminal connected to the second node, a second terminal, and a gate terminal connected to the first node;
- a seventh NMOS transistor including a first terminal connected to the second terminal of the third NMOS transistor, a second terminal connected to a sixth node, and a gate terminal configured to receive the clock signal;
- an eighth NMOS transistor including a first terminal connected to the second terminal of the sixth NMOS transistor, a second terminal connected to a fifth node, and a gate terminal configured to receive the clock signal;
- a ninth PMOS transistor including a first terminal connected to the third node, a second terminal connected to the sixth node, and a gate terminal connected to the fifth node;
- a ninth NMOS transistor including a first terminal connected to the sixth node, a second terminal connected to the low power voltage, and a gate terminal connected to the fifth node;
- a fifteenth NMOS transistor including a first terminal connected to the sixth node, a second terminal connected to the low power voltage, and a gate terminal configured to receive the set signal;
- a tenth PMOS transistor including a first terminal connected to the fourth node, a second terminal connected to the fifth node, and a gate terminal connected to the sixth node;
- a tenth NMOS transistor including a first terminal connected to the fifth node, a second terminal connected to the low power voltage, and a gate terminal connected to the sixth node;
- an eleventh PMOS transistor including a first terminal connected to the high power voltage, a second terminal connected to an output node, and a gate terminal connected to the sixth node;
- and
- an eleventh NMOS transistor including a first terminal connected to the output node, a second terminal connected to the low power voltage, and a gate terminal connected to the sixth node,
- said flip-flop being configured to,
- latch the input data at rising edges of the clock signal, and to output the latched input data as output data at the output node, and
- set the output data to have a logic ‘high’ level in response to the set signal having a logic ‘high’ level.
27 more elements
Dependencies are inferred from the claim text.