Semiconductor Device
AssigneeSamsung Electronics Co., Ltd.
InventorsByoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
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Abstract
A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.
Claims21
A semiconductor device comprising:
- a multi-channel active pattern on a substrate;
- a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal;
- a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer;
- and
- a gate electrode on the silicon nitride layer.
A semiconductor device comprising:
- a multi-channel active pattern on a substrate;
- a gate insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the gate insulating layer comprises a boundary layer and a high dielectric constant insulating layer;
- and
- a gate electrode structure on the gate insulating layer,
- wherein the gate electrode structure comprises a work function adjusting liner which is in contact with the gate insulating layer,
- a dielectric constant of the work function adjusting liner is less than a dielectric constant of the high dielectric constant insulating layer, and
- a thickness of the work function adjusting liner is less than a thickness of the high dielectric constant insulating layer.
A semiconductor device comprising:
- a first nanowire on a substrate;
- a second nanowire spaced apart from the first nanowire on the first nanowire;
- a gate insulating layer formed along a periphery of the first nanowire and a periphery of the second nanowire on the first nanowire and the second nanowire, wherein the gate insulating layer comprises a metal;
- a silicon nitride layer formed along the periphery of the first nanowire and the periphery of the second nanowire on the gate insulating layer and being in contact with the gate insulating layer;
- and
- a gate electrode which comprises a conductive liner containing titanium on the silicon nitride layer, the conductive liner comprising a gate electrode formed along the periphery of the first nanowire and the periphery of the second nanowire.
-36. (canceled)
Dependencies are inferred from the claim text.