Formation of air gap spacers for reducing parasitic capacitance

A method for reducing parasitic capacitance, the method comprising:

• forming a source region and a drain region within a substrate;
• forming spacers in direct contact with sidewalls of a sacrificial layer;
• depositing an inter-layer dielectric (ILD) over the source and drain regions;
• replacing the sacrificial layer with a gate structure;
• removing the ILD and the spacers;
• depositing a sacrificial dielectric layer;
• removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions;
• depositing a conductive material over the exposed top surfaces of the source and drain regions;
• removing remaining portions of the sacrificial dielectric layer to form trenches on opposed ends of the conductive material;
• depositing a dielectric liner;
• and
• depositing an oxide within the trenches to form air gap spacers between the gate structure and the source and drain regions.

A semiconductor structure for reducing parasitic capacitance, the semiconductor structure comprising:

• a source region and a drain region disposed within a substrate;
• spacers disposed in direct contact with sidewalls of a gate structure;
• a conductive material disposed in direct contact with top surfaces of the source and drain regions;
• and
• a dielectric material disposed on opposed ends of the conductive material such that air gap spacers are created between the gate structure and the source and drain regions.