Nanosheet single gate (sg) and extra gate (eg) field effect transistor (fet) co-integration

A method of forming an electrical device comprising:

• providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness, wherein the second thickness is less than the first thickness;
• forming a dielectric layer on the first and second stack of nanosheets, wherein the dielectric layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack;
• removing the dielectric layer from the first stack of nanosheets to open the space between the nanosheets in the first stack, wherein the dielectric layer remains conformally present on the nanosheets in the second stack;
• and
• forming a work function metal layer on the first and second stack of nanosheets, the work function metal layer is present filling an entirety of the space between the nanosheets in the first stack, and the work function metal layer is conformally present about an entirety of the nanosheets in the second stack, wherein a space remain between stacked nanosheets in the second stack.

A method of forming an electrical device comprising:

• providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness, wherein the second thickness is less than the first thickness;
• forming a metal nitride layer on the first and second stack of nanosheets, wherein the metal nitride layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack;
• removing the metal nitride layer from the second stack of nanosheets;
• forming a dielectric layer on the second stack of nanosheets;
• removing the metal nitride layer from the first stack of nanosheets;
• and
• forming a work function metal layer on the first and second stack of nanosheets, wherein the work function metal layer is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.