Semiconductor devices having a gate isolation layer and methods of manufacturing the same

A semiconductor device comprising:

• a substrate comprising a channel region that protrudes from the substrate;
• a gate line on a first side surface and a second side surface of the channel region;
• gate spacers on a first side surface and a second side surface of the gate line;
• and
• a gate isolation layer in a gate cut region that separates a first portion of the gate line from a second portion of the gate line,
• wherein the gate isolation layer is in contact with the gate line and comprises a gap that is in the gate isolation layer,
• wherein a first width of the gap is greater than a second width of the gap,
• wherein a third width of the gap is narrower than the first width, and
• wherein the first width is between the second width and the third width.

A semiconductor device comprising:

• a substrate comprising a channel region that protrudes from the substrate and that extends in a first direction;
• a first gate line and a second gate line that are on the channel region and that extend in a second direction intersecting the first direction, wherein the first gate line is spaced apart from the second gate line in the first direction;
• gate spacers on a first side surface and a second side surface of the first gate line;
• a gate insulating layer between the first gate line and the gate spacers;
• a gate isolation layer in a gate cut region that is between the first gate line and the second gate line in the first direction;
• and
• a gap in the gate isolation layer,
• wherein the gate cut region separates the first gate line, separates the gate insulating layer, and separates the gate spacers,
• wherein the gate isolation layer is in contact with the first gate line, and
• wherein a first width of the gate isolation layer is greater than, and located between, a second width and a third width of the gate isolation layer.