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US 2019/0378892 A1Published application
Hybrid High and Low Stress Oxide Embedded Capacitor Dielectric
AssigneeTexas Instruments Incorporated
InventorsElizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield
Life of this patent
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Abstract
An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.
Claims26
An integrated circuit, comprising:
- a metal top plate located over a substrate;
- a metal bottom plate located between the top plate and the substrate;
- a high-stress silicon dioxide layer located between the bottom plate and the substrate;
- and
- at least one low-stress silicon dioxide layer located between the top plate and the bottom plate.
2 more elements
A method of forming an integrated circuit, comprising:
- forming a metal top plate over a substrate;
- forming a metal bottom plate between the top plate and the substrate;
- forming a high-stress silicon dioxide layer between the bottom plate and the substrate;
- and
- forming at least one low-stress silicon dioxide layer between the top plate and the bottom plate.
2 more elements
An integrated circuit, comprising:
- a semiconductor substrate having top and bottom metal plates formed thereover, the bottom plate located between the top plate and the substrate;
- a first HDP oxide layer formed over and touching the bottom metal plate;
- a first low-stress silicon dioxide layer located over and touching the HDP oxide layer;
- a first high-stress silicon dioxide layer located over and touching the low-stress silicon dioxide layer;
- a second HDP oxide layer formed over and touching the first high-stress silicon dioxide layer;
- a second low-stress silicon dioxide layer located over and touching the second HDP oxide layer;
- and
- a second low-stress silicon dioxide layer located over and touching the second HDP oxide layer.
5 more elements
An integrated circuit, comprising:
- a semiconductor substrate having top and bottom metal plates formed thereover, the bottom plate located between the top plate and the substrate;
- a first HDP oxide layer formed between the bottom plate and the top plate, the first HDP oxide layer touching the bottom metal plate;
- a first high-stress silicon dioxide layer located over and touching the HDP oxide layer;
- a second HDP oxide layer formed over the first high-stress silicon dioxide layer;
- a second high-stress silicon dioxide layer located over and touching the second HDP oxide layer;
- and
- a low-stress silicon dioxide layer located over and touching the second high-stress silicon dioxide layer.
4 more elements
Dependencies are inferred from the claim text.