Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device comprising:

• memory cell array regions disposed on a base substrate;
• first and second inner stepped regions between the memory cell array regions;
• a bridge region between the first and second inner stepped regions;
• a gate stacked structure including first and second word lines stacked in the memory cell array regions and extending lengthwise in a first direction to the first and second inner stepped regions;
• and
• a through region passing through the gate stacked structure in the bridge region,
• wherein each of the first and second word lines extend lengthwise from the memory cell array regions and connect in the bridge region, and
• wherein a length in the first direction of the gate stacked structure disposed in the first inner stepped region is different from a length in the first direction of the gate stacked structure disposed in the second inner stepped region.

A three-dimensional semiconductor memory device comprising:

• first and second gate stacked structures stacked on a base substrate;
• and
• a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures,
• wherein the first and second gate stacked structures comprise first and second word lines, respectively,
• wherein the first word lines of the first gate stacked structure include first contact pads surrounding the through region and disposed in a first stepped shape that lowers toward the through region, and the second word lines of the second gate stacked structure include second contact pads surrounding the through region and disposed in a second stepped shape that lowers toward the through region, and
• wherein the second contact pads cover a portion of the first contact pads.