US 2019/0378848 A1Published application

Low cost multiple-time programmable cell on silicon on insulator technology and method for producing the same

AssigneeGlobalfoundries Singapore Pte. Ltd.

InventorsEng Huat TOH, Shyue Seng TAN, Danny Pak-Chum SHUM

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Abstract

A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.

Claims20

Dependent claims

A method comprising:

forming a bulk region in a portion of a silicon on insulator (SOI) wafer;
forming an n-type well (NW) in the bulk region in a silicon (Si) substrate of the SOI wafer and a p-type well (PW) in the Si substrate of a remaining SOI region of the SOI wafer;
forming a first pair of common floating gate (FG) stacks and a second pair of common FG stacks over both of the SOI region and the bulk region, each common FG stack over a portion of the NW and over and perpendicular to a portion of the PW;
forming a first shared N+ raised source/drain (RSD) between each common FG stack of the first pair and the second pair in a top Si layer of the SOI wafer in the SOI region;
forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD;
forming a second shared N+ RSD between each common FG stack of the first pair and the second pair in the Si substrate of the bulk region;
and
forming a P+ RSD between the first pair and the second pair in the Si substrate of the bulk region.

5 more elements

A device comprising:

a bulk region in a portion of a silicon on insulator (SOI) wafer;
an n-type well (NW) in the bulk region in a silicon (Si) substrate of the SOI wafer and a p-type well (PW) in the Si substrate of a remaining SOI region of the SOI wafer;
a first pair of common floating gate (FG) stacks and a second pair of common FG stacks over both of the SOI region and the bulk region, each common FG stack over a portion of the NW and over and perpendicular to a portion of the PW;
a first shared N+ raised source/drain (RSD) between each common FG stack of the first pair and the second pair in the SOI region in a top Si layer of the SOI wafer;
a second shared N+ RSD in the top Si layer on an opposite side of each common FG from the first shared N+ RSD;
a select gate (SG) stack, each SG stack over a portion of the PW on an opposite side of the second shared N+ RSD from the first shared N+ RSD;
a N+ RSD in the top Si layer on an opposite side of the SG stack from the second shared N+ RSD;
a third shared N+ RSD in the top Si substrate of the bulk region between each common FG of the first pair and the second pair;
and
a P+ RSD between the first pair and the second pair in the Si substrate of the bulk region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/001,485Filed 6 Jun 2018
Published: 12 Dec 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10D 87/00
Integrated devices comprising both bulk components and either soi or sos components
G11C 16/0441
Comprising cells containing floating gate transistors: comprising cells containing multiple floating gate devices, e.g. separate read-and-write…
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits

Family

US 10,685,970 B2Related patent
US 2019/0378848 A1This patent

From the US filing history. Foreign family members aren’t listed.

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