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US 2019/0378820 A1Published application
Interlayer connection of stacked microelectronic components
AssigneeInvensas Bonding Technologies, Inc.
InventorsGuilian Gao, Belgacem Haba
Life of this patent
Estimating the term…
Abstract
Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.
Claims24
A method of forming a microelectronic assembly, comprising:
- forming a conductive pad at a first relative position on a surface of each of a plurality of microelectronic substrates;
- stacking the plurality of microelectronic substrates to form a vertical stack of microelectronic substrates while vertically aligning the conductive pad at each microelectronic substrate;
- etching one or more layers of at least all but one of the microelectronic substrates to form a cavity extending through the at least all but one of the microelectronic substrates, the cavity adjacent to a portion of the conductive pad on each of the microelectronic substrates;
- and
- filling the cavity with a conductive material to form a through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack, the TSV comprising an interlayer connection electrically coupling the conductive pad at each microelectronic substrate.
2 more elements
A method of forming a microelectronic assembly, comprising:
- forming a conductive pad at a first relative position on a surface of each of a plurality of microelectronic substrates, the conductive pad including an interior area free of conductive material;
- stacking the plurality of microelectronic substrates to form a vertical stack of microelectronic substrates while vertically aligning the conductive pad at each microelectronic substrate;
- etching one or more layers of at least all but one of the microelectronic substrates to form a cavity extending through at least all but one of the microelectronic substrates, the cavity adjacent to a portion of the conductive pad and extending through the interior area of the conductive pad of the at least all but one of the microelectronic substrates;
- and
- filling the cavity with a conductive material to form a through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack, the TSV comprising an interlayer connection electrically coupling the conductive pad at each microelectronic substrate.
2 more elements
A microelectronic assembly, comprising:
- a plurality of microelectronic substrates stacked to form a vertical stack;
- a conductive pad disposed at a first relative position on a surface of each of the microelectronic substrates, conductive pads of each of the microelectronic substrates vertically aligned while the plurality of microelectronic substrates form the vertical stack;
- a cavity extending through at least all but one of the microelectronic substrates, the cavity adjacent to a portion of the conductive pad of each of the microelectronic substrates;
- and
- a conductive material within the cavity forming a through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack, the TSV comprising an interlayer connection electrically coupled to the conductive pad of each of the microelectronic substrates.
2 more elements
Dependencies are inferred from the claim text.